Design and simulation of a VLIW processor

被引：0

作者：

Otani, K ^{[1
]}

Sakai, K ^{[1
]}

Ae, T ^{[1
]}

机构：

[1] Hiroshima Univ, Fac Engn, Higashihiroshima 7398527, Japan

来源：

INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-IV, PROCEEDINGS | 1998年

关键词：

VLIW; performance evaluation; iDCT; z-buffer;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We are developing a simulator for performance evaluation of VLIW processor. Due to examples of performance evaluation, we evaluate and design, a VLIW processor for multimedia date, processing. The VLIW processor includes four function units with hardware stack each. We focus on the iDCT routine and the z-buffer routine for performance evaluation of multimedia data processing. As a result, we have designed a. VLSI chip of the first-version VLIW processor (SBG: Slack-Based Computer) by Verilog-HDL.

引用

页码：1459 / 1466

页数：8

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