Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and Beyond

被引：0
|
作者：
Yang, Xiaoqiao [1 ]
Sun, Yabin [1 ]
Liu, Ziyu [2 ]
Shi, Yanling [1 ]
Li, Xiaojin [1 ]
机构：
[1] East China Normal Univ, Dept Elect Engn, Shanghai 200241, Peoples R China
[2] Fudan Univ, Sch Microelect, Shanghai 200433, Peoples R China
来源：
2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM) | 2021年
基金：
中国国家自然科学基金;
关键词：
CFET; gate-all-around (GAA); TCAD;
D O I：
10.1109/EDTM50988.2021.9420820
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A comparative analysis of DC/AC performance of complementary FET (CFET) is presented by 3D TCAD simulation for 3nm-node and beyond. Three types of device architectures with different structure parameters are investigated and compared on some critical electrical characteristics. Through adjusting the fin height and width, the source/drain-extension-to-gate underlap length and the n-/p-FET separator thickness and material, the tradeoff between DC and AC performance is shown to give an optimized CFET device architecture.
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页数：3
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