Compiler support for low-cost synchronization among threads

Traditional compilation techniques for synchronization have targeted architectures with relatively high synchronization overhead, and have been used to synchronize loops or different processes at a coarse granularity. Processors will soon be available that have multiple, tightly-coupled instruction streams on a single chip, and these processors will support the exploitation of finer-grained parallelism among threads of a single process, e.g. through simultaneous multithreading. This paper proposes synchronization techniques for such architectures. These techniques are unique in their support for architectures with extremely low synchronization overhead and for overlapping different loop nests. The proposed techniques account for underlying communication costs, and make trade-offs between reducing synchronization overhead and maximizing parallelism. These techniques have been implemented in the Pedigree post-pass compiler.