Model-Driven Design of Network Aspects of Distributed Embedded Systems

被引:11
|
作者
Ebeid, Emad [1 ]
Fummi, Franco [2 ,3 ]
Quaglia, Davide [2 ,3 ]
机构
[1] Aarhus Univ, Dept Engn, DK-8200 Aarhus, Denmark
[2] Univ Verona, EDALab Srl, I-37134 Verona, Italy
[3] Univ Verona, Dept Comp Sci, I-37134 Verona, Italy
关键词
Modeling and analysis of real time and embedded systems (MARTE); network manipulation; network synthesis; simulation; SystemC/transaction level modeling (TLM); unified modeling language (UML); UML;
D O I
10.1109/TCAD.2015.2394395
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Design of distributed embedded systems is a challenging task and it requires raising the level of abstraction to overcome the complexity of the design. In particular, modeling languages and semantic specification are necessary to address network description at high level of abstraction. Starting from this abstraction view, model manipulation is needed to explore various design alternatives and code generation is required for their simulation. In this paper, we propose the use of unified modeling language diagrams combined with a formal computational model as a key solution to specify requirements, generate design alternatives, and code for simulation. This paper proposes a formal framework and supporting tools to represent the application requirements, the library of network components, the environment description, and the rules to compose them. The framework allows to generate code for design validation by simulation and provides back annotation mechanism of the simulation results to refine the original model.
引用
收藏
页码:603 / 614
页数:12
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