A Simulated Annealing Based Technology Mapping Method for Sequential Circuits

被引：0

作者：

Li, Peng ^{[1
]}

Lan, Julong ^{[1
]}

Li, Dan ^{[1
]}

Liu, Qiang ^{[1
]}

机构：

[1] Natl Digital Switching Syst Engn & Technol Res Ct, Zhengzhou 450002, Peoples R China

来源：

2009 FIRST INTERNATIONAL CONFERENCE ON FUTURE INFORMATION NETWORKS | 2009年

关键词：

pipeline; sequential technology mapping; simulated annealing; retiming;

D O I：

10.1109/ICFIN.2009.5339593

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Due to the rapid growth of traffic in Internet, backbone links of 40 gigabits per second are commonly deployed. To handle high traffic rates, the backbone routers must be able to forward millions of packets per second on each of their ports. Pipe lined design can effectively support high speed packets processing. Technology mapping method for sequential circuits in FPGA is playing vital role to pipelined design. This paper presents a simulated annealing based technology mapping method for sequential circuits. The proposed method not only guarantees minimal clock period for pipeline level, but also saves FPGA resources.

引用

页码：303 / 307

页数：5

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