A new framework for power estimation of embedded systems

Among the many metrics used to characterize the quality of an embedded system-on-chip design, power consumption has emerged as one of the most important. This is largely due to the proliferation of mobile battery-powered computing devices, the increasing speed and density of CMOS (complementary metal-oxide semiconductor) VLSI (very large-scale integration) circuits, and continuous shrinking of the transistor feature size of deep-submicron technologies. The authors have developed a technique that derives power figures from the execution of high-level models. This technique makes it possible to assess embedded SoC designs much earlier in the design cycle, contributing to sounder decisions throughout the entire development process and leading to a faster execution time. To validate their methodology, the authors applied it to a peripheral core-a baud rate generator-and compared the results with those obtained using a gate-level approach.