An analytical model for reliability evaluation of NoC architectures

被引：18
|
作者：
Dalirsani, Atefe [1 ]
Hosseinabady, Mohammad [1 ]
Navabi, Zainalabedin [1 ]
机构：
[1] Univ Tehran, Nanoelectr Ctr Excellence, Tehran 14399, Iran
来源：
13TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM PROCEEDINGS | 2007年
关键词：
D O I：
10.1109/IOLTS.2007.13
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. The proposed method classifies switch faults of an NoC according to their impact on system functionality. Based on this classification, the contribution of each transient fault lowering the reliability of the NoC is calculated. This model can be used to decide which fault tolerant techniques cause more improvement on system reliabiliry.
引用
收藏
页码：49 / 54
页数：6
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