Simulation of active-matrix electrophoretic display response time optimization by dual-gate a-Si:H TFT with a common gate structure

Large off-state drain-source current of the thin-film transistor (TFT) in active-matrix electrophoretic display (AMEPD) pixel leads to dramatic data voltage degradation, which causes severe crosstalk and undesired large response time. In this paper, the leakage current influence on response time is investigated and simulated. A compact model of response time t versus off-state drain-source current I-off is established. The simulation result induces that by reducing I-off, the response time can be efficiently shorted. In order to reduce the off-state current, dual-gate amorphous silicon (a-Si:H) TFT with a common gate structure is discussed. Its current regulation mechanism is illustrated, and its fitness for driving the AMEPD pixel is explained. The SPICE simulation results prove that except reducing the crosstalk, dual-gate a-Si TFT can also significantly short the response time by cutting down the off-state current under the operation conditions of AMEPD application, while insignificantly reduces the on-state current.