Closing the gap between analog and digital testing

被引：18
|
作者：
Saab, K [1 ]
Ben Hamida, N
Kaminska, B
机构：
[1] Adapt Networks Inc, Newton, MA 02459 USA
[2] Nortel Networks, Ottawa, ON K1P 6A6, Canada
[3] Fluence Technol Inc, Beaverton, OR 97008 USA
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2001年 / 20卷 / 02期
关键词：
analog and mixed circuits; fault modeling; hard faults testing; parallel fault simulation; test vector generation;
D O I：
10.1109/43.908473
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a highly effective method for parallel hard fault simulation and test-specification development. The proposed method formulates the fault-simulation problem as a problem of estimating the fault value based on the distance between the output parameter distribution of the fault-free and the faulty circuit. We demonstrate the effectiveness and practicality of our proposed method by showing results on different designs, This approach, extended by parametric fault testing, has been implemented as an automated tool set for integrated circuit (IC) testing.
引用
收藏
页码：307 / 314
页数：8
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