共 50 条
- [2] High Performance Stencil Code Generation with LIFT [J]. PROCEEDINGS OF THE 2018 INTERNATIONAL SYMPOSIUM ON CODE GENERATION AND OPTIMIZATION (CGO'18), 2018, : 100 - 112
- [3] Evaluation of Programming Models and Performance for Stencil Computation on GPGPUs [J]. 2024 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS, IPDPSW 2024, 2024, : 1178 - 1180
- [4] Understanding Stencil Code Performance On MultiCore Architectures [J]. PROCEEDINGS OF THE 2011 8TH ACM INTERNATIONAL CONFERENCE ON COMPUTING FRONTIERS (CF 2011), 2011,
- [5] A new memory mapping mechanism for GPGPUs’ stencil computation [J]. Computing, 2015, 97 : 795 - 812
- [6] A new memory mapping mechanism for GPGPUs' stencil computation [J]. COMPUTING, 2015, 97 (08) : 795 - 812
- [7] High Performance Code Generation for Stencil Computation on Heterogeneous Multi-device Architectures [J]. 2013 IEEE 15TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS & 2013 IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND UBIQUITOUS COMPUTING (HPCC_EUC), 2013, : 1512 - 1518
- [8] High Performance Parallel Graph Coloring on GPGPUs [J]. 2016 IEEE 30TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 2016, : 845 - 854
- [10] Evaluating optimizations that reduce global memory accesses of stencil computations in GPGPUs [J]. CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2019, 31 (18):