Fault-aware and Reconfigurable Routing Algorithms for Networks-on-Chip

Currently, the manufacturing process of complex systems such as network-based Systems-on-Chip incurs a considerable amount of failures. This paper presents a class of very low cost routing algorithms to increase the yield and to tolerate permanent faulty links in Networks-on-Chip. These new algorithms are fault tolerant through dynamic reconfiguration when the regular topology is altered by faulty links. Also, the proposed algorithms are the reconfigurable extensions of deterministic routing algorithms and their deadlock freeness is obtained by prohibiting a few turns. To demonstrate the effectiveness of the proposed routing algorithms, the performance, power consumption, and area overheads are evaluated through appropriate simulations and syntheses. The experimental results show that considerable reliability and yield improvements are obtained with only a few percent power and area overheads.