A low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder

被引：0
|
作者：
Tsai, TH [1 ]
Chen, LG [1 ]
Huang, SC [1 ]
Chang, HC [1 ]
机构：
[1] Natl Taiwan Univ, Dept Elect Engn, Taipei, Taiwan
来源：
ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-forths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.
引用
收藏
页码：C65 / C68
页数：4
相关论文
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