Moving images time gradient implementation using RAM-based FPGA

被引:1
|
作者
Nozal, LL
Aranguren, G
Martin, JL
Ezquerra, J
机构
来源
REAL-TIME IMAGING II | 1997年 / 3028卷
关键词
moving images; time gradient; Field Programmable Gate Array; video rate; 3D mask; visual motion; image sequences; hardware for image processing;
D O I
10.1117/12.270337
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Time gradient can be used to extract information from motion. It has been already done, but higher performances are reached if it's computed on real time (at video rate). We propose an architecture to evaluate it from consecutive images in a video signal. Behind a delaying structure, a circuit operates over the neighbourhood of pixels around each one: not only the adjacent pixels in space but also in time (in several previous images), Gradient can be extracted from all of them by convolution, and other non-linear algorithms can also be applied. Known 3x3 masks to operate over static images are generalized by 3D masks (3x3x3) to operate over dynamic images. The circuit is based on Field Programmable Gate Array (FPGA) devices, them, a set of specific purpose hardware designs can be loaded on RAM cells in FPGA, so it's fast as hardware and versatile as software, and different approaches of gradient can be implemented from host computer to programmable logic in FPGA.
引用
收藏
页码:108 / 116
页数:9
相关论文
共 50 条
  • [1] TRACER-FPGA - A ROUTER FOR RAM-BASED FPGAS
    CHEN, CD
    LEE, YS
    WU, ACH
    LIN, YL
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (03) : 371 - 374
  • [2] Low Power RAM-Based Hierarchical CAM on FPGA
    Qian, Zhuo
    Margala, Martin
    [J]. 2014 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2014,
  • [3] Test of RAM-based FPGA: Methodology and application to the interconnect
    Renovell, M
    Figueras, J
    Zorian, Y
    [J]. 15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, : 230 - 237
  • [4] RAM-based programmable stack filter implementation
    Hu, M
    Vainio, O
    Astola, J
    Egiazarian, K
    Gevorkian, D
    [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING, 1999, : 474 - 477
  • [5] A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher
    Kitsos, P
    Galanis, MD
    Koufopavlou, O
    [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4641 - 4644
  • [6] RAM-BASED TONE MAPPING FOR HIGH DYNAMIC RANGE IMAGES
    Shen, Jianbing
    Sun, Hanqiu
    Zhao, Hanli
    Jin, Xiaogang
    [J]. ICME: 2009 IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXPO, VOLS 1-3, 2009, : 1110 - +
  • [7] RAM-based FPGA's: A test approach for the configurable logic
    Renovell, M
    Portal, JM
    Figueras, J
    Zorian, Y
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, : 82 - 88
  • [8] A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry
    Khaleghi, Behnam
    Asadi, Hossein
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65 (07) : 2196 - 2209
  • [9] Generalization and Implementation of RAM-Based Key-Value Store
    Tian, Tian
    Zhang, Chengfei
    Yu, Kai
    Zhang, Yiming
    Zhong, Ping
    [J]. 2016 INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE & COMPUTATIONAL INTELLIGENCE (CSCI), 2016, : 1412 - 1413
  • [10] A Reconfigurable Pattern Matching Hardware Implementation using On-Chip RAM-Based FSM
    Rafla, Nader I.
    Gauba, Indrawati
    [J]. 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 49 - 52