Design and implementation of a new built-in self-test boundary scan architecture

被引：0
|
作者：
El-Mahlawy, MH
El-Sehely, EA
Ragab, AES
Anas, S
机构：
来源：
ICM 2003: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2003年
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中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The boundary scan (BS) technique offers a convenient alternative to physical probing. This paper presents new boundary scan architecture for Built-In Self-Test (BIST). The Boundary Scan Register (BSR) input cells have been configured to operate as a Test Pattern Generator (TPG) in the BIST mode. The BSR output cells have been configured to operate as a Muti-Input Shift Register (MISR) in the BIST mode. The Test Access Port Controller (TAPC) controls the BIST process. Instructions for BIST process are proposed. This configuration supports the BIST for both the Built-In Logic Block Observer (BILBO) register and the register transfer level. This design implemented on the Field Programmable Gate Array (FPGA) Spartan X2C200 family.
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页码：27 / 31
页数：5
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