Efficiency Based Design Flow for Fully-Integrated Class C RF Power Amplifiers in Nanometric CMOS

In this work a design flow for class C radiofrequency (RF) power amplifiers (PA) with on-chip output networks in nanometric technologies is presented. This is a new parasitic-aware method intended to reduce time-consuming iterations which are normally required in fully-integrated designs. Unlike other methods it is based on actual transistors DC characteristics and inductors data -both extracted by simulation-. Starting from the output power specifications a design space map is generated showing the trade-offs between efficiency and components sizing, thus enabling the selection of the most appropriate design that satisfies the harmonic distortion requirements. As a proof of concept of the proposed method, a design example for an IEEE 802.15.4 2.4 GHz PA in a 90 nm CMOS technology is presented.