Sparse Graph Processing with Soft Processors

Modern FPGAs can be configured to exploit the large amount of onchip parallelism possible from the distributed SRAM memory blocks for algorithms operating on large sparse graphs. To simplify the programming and configuration of such memory-centric organizations, we can customize an array of soft processors for these graph algorithms. In particular, we can deliver significant performance improvements for bulk synchronous graph algorithms with a custom processor that implements a graph-specific ISA. We develop a C++ API using Vivado High-Level Synthesis to describe graph computations and generate custom soft processors from these high-level descriptions. Our preliminary experiments suggest that our soft processor outperform Microblaze and NIOS-II/f soft processors by approximate to 6x. While not the focus of this work, this design can scale out to a cluster of 1632 low-power, energy-efficient Zedboards and Microzedboards to compete with server-class x86 nodes.