The hardware results of a 64x64 analog input array for a 3-dimensional neural network processor

被引：0
|
作者：
Duong, TA [1 ]
Thomas, T [1 ]
Daud, T [1 ]
Thakoor, A [1 ]
Suddarth, S [1 ]
机构：
[1] CALTECH, Jet Prop Lab, Ctr Space Microelect Technol, Pasadena, CA 91109 USA
来源：
IEEE WORLD CONGRESS ON COMPUTATIONAL INTELLIGENCE | 1998年
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D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
引用
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页码：593 / 597
页数：5
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