Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell

被引:16
|
作者
Shino, T [1 ]
Ohsawa, T [1 ]
Higashi, T [1 ]
Fujita, K [1 ]
Kusunoki, N [1 ]
Minami, Y [1 ]
Morikado, M [1 ]
Nakajima, H [1 ]
Inoh, K [1 ]
Hamamoto, T [1 ]
Nitayama, A [1 ]
机构
[1] Toshiba Co Ltd, SoC Res & Dev Ctr, Yokohama, Kanagawa 2358522, Japan
关键词
distribution; MOSFETs; random access memories; silicon-on-insulator (SOI) technology; threshold voltage;
D O I
10.1109/TED.2005.856808
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state and the "1"-state, which is a key parameter for realizing a larger scale memory by FBCs, is measured and analyzed using a 96 kb array diagnostic monitor (ADM). A function test of the ADM yielded a fail-bit probability of 0.002%. A new metric relating to the fail-bit probability, that is, the ratio of the threshold voltage difference over the total threshold voltage variation, is introduced and applied to the measurement results. Read current distributions are also evaluated for various operation voltages. This paper also investigates substrate bias dependence of the threshold voltage unique to fully-depleted devices. Channel impurity and substrate impurity concentration dependence of the threshold voltage are analyzed based on experimental data and device simulation.
引用
收藏
页码:2220 / 2226
页数:7
相关论文
共 50 条
  • [1] Methodology for flatband voltage measurement in fully depleted floating-body FinFETs
    Ferain, Isabelle
    Pantisano, Luigi.
    O'Sullivan, Barr J.
    Singanamalla, Raghunath
    Collaert, Nadine
    Jurczak, Malgorzata
    De Meyer, Kristin
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (07) : 1657 - 1663
  • [2] Carrier Lifetime Engineering for Floating-Body Cell Memory
    Kim, Sungho
    Choi, Sung-Jin
    Moon, Dong-Il
    Choi, Yang-Kyu
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (02) : 367 - 373
  • [3] A Novel Two-Transistor Floating-Body Memory Cell
    Fossum, J. G.
    Lu, Z.
    Zhang, W.
    Trivedi, V. P.
    Mathew, L.
    Sadd, M.
    2007 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 2007, : 91 - +
  • [4] Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs
    Chan, M
    Su, P
    Wan, H
    Lin, CH
    Fung, SKH
    Niknejad, AM
    Hu, CM
    Ko, PK
    SOLID-STATE ELECTRONICS, 2004, 48 (06) : 969 - 978
  • [5] Persistent Floating-Body Effects in Fully Depleted Silicon-on-Insulator Transistors
    Park, Hyungjin
    Colinge, Jean-Pierre
    Cristoloveanu, Sorin
    Bawedin, Maryline
    PHYSICA STATUS SOLIDI A-APPLICATIONS AND MATERIALS SCIENCE, 2020, 217 (09):
  • [6] On the temperature dependence of hysteresis effect in floating-body partially depleted SOICMOS circuits
    Puri, R
    Chuang, CT
    Ketchen, MB
    Pelella, MM
    Rosenfield, MG
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (02) : 290 - 298
  • [7] ANALYSIS AND CONTROL OF FLOATING-BODY BIPOLAR EFFECTS IN FULLY DEPLETED SUBMICROMETER SOI MOSFETS
    CHOI, JY
    FOSSUM, JG
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1991, 38 (06) : 1384 - 1391
  • [8] Modeling of anomalous current-voltage characteristics in floating body fully depleted SOI nMOSFETs
    Feng Chia Univ, Taichung, Taiwan
    Solid State Electron, 5 (713-720):
  • [9] Modeling of anomalous current-voltage characteristics in floating body fully depleted SOI nMOSFETs
    Yang, PC
    Liu, PS
    SOLID-STATE ELECTRONICS, 1996, 39 (05) : 713 - 720
  • [10] A Simplified Superior Floating-Body/Gate DRAM Cell
    Lu, Zhichao
    Fossum, Jerry G.
    Yang, Ji-Woon
    Harris, H. Rusty
    Trivedi, Vishal R.
    Chu, Min
    Thompson, Scott E.
    IEEE ELECTRON DEVICE LETTERS, 2009, 30 (03) : 282 - 284