Implementation of 10bit SerDes for Gigabit Ethernet PHY

被引：0

作者：

Samanta, Smrutilekha ^{[1
]}

Dastidar, Ananya ^{[1
]}

机构：

[1] BPUT, Ctr Adv Post Grad Studies, Dept Elect & Commun Engn, Rourkela, Odisha, India

来源：

PROCEEDINGS 2015 INTERNATIONAL CONFERENCE ON MAN AND MACHINE INTERFACING (MAMI) | 2015年

关键词：

SerDes; Ethernet; SIPO; PISO;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Serializer/Deserializer (SerDes) is a pair of functional block which play a vital role in many electronic devices used for high speed communication. The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block and the Serial In Parallel Out (SIPO) block. An efficient SerDes offer high speed and low power consumption. In this paper an attempt is made to optimize the design for high speed and low power SerDes for wideband communication such as Ethernet applications. The power consumption and data transfer rate of the proposed design was calculated to be 737 mWand 25Gb/s respectively.

引用

页数：5

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