This paper proposes a new model for a reconfigurable mesh, in which reconfigurability of individual nodes is exploited. A node of an n-dimensional reconfigurable mesh is fitted with n internal buses and 2n. external ports. Each port can either drive each bus or be driven by it. Driver circuits are reconfigurable, achieving the effect of a node with reconfigurable switches. Examples of reconfigurable drivers are given with exclusive-or drivers one of 16 2-input logical operations, and one of 256 3-input logical operations. Constant time algorithms on these meshes are introduced: logical and exclusive or parallel prefix, addition and prefix-sums of n bits, and a q-bit n-integer adder. This model is also a realization of nonmonotonic reconfigurable networks introduced by Ben-Asher, Peleg, Ramaswami and Schuster, where switches can take additional functions besides data copy, such as "not" and "or".