A power estimation model for an FPGA-based softcore processor

被引:2
|
作者
Zipf, Peter [1 ]
Hinkelmann, Heiko [1 ]
Deng, Lei [1 ]
Glesner, Manfred [1 ]
Blume, Holger [2 ]
Noll, Tobias G. [2 ]
机构
[1] Tech Univ Darmstadt, Inst Microelect Syst, Darmstadt, Germany
[2] Rhein Westfal TH Aachen, Elect Engn & Comp syst, Aachen, Germany
关键词
D O I
10.1109/FPL.2007.4380643
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
We describe the application of a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach to a processor model implemented on an FPGA. This technique enables the estimation of the task specific power consumption of the modeled processor, in our case a LEON2, very early during a system design flow, based on the software which will run on it. The FLPA/ILPA model used during our work as well as the test scenarios and the measured results are described. Later, the function block separation and the power consumption modeling are discussed. Finally, the model is validated by benchmarking. The obtained model is promising in the sense that a) its estimations are close (4 % on average) to the measured data, and b) the model structure is similar to that of hardcore processors which is not a trivial result.
引用
收藏
页码:171 / 176
页数:6
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