Pipelined Architecture for Discrete Wavelet Transform Implementation on FPGA

被引：1
|
作者：
Bahoura, Mohammed [1 ]
Ezzaidi, Hassan [2 ]
机构：
[1] Univ Quebec, Dept Engn, 300 Allee Ursulines, Rimouski, PQ, Canada
[2] Univ Quebec Chicoutimi, Dept Appl Sci, Chicoutimi, PQ, Canada
来源：
2010 INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2010年
关键词：
VLSI ARCHITECTURE;
D O I：
10.1109/ICM.2010.5696188
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we propose a pipelined real-time architecture for forward/inverse wavelet transforms that take into account the filter group delays. The required resources and the reconstruction error of this architecture were evaluated and compared to those of the conventional one. These architectures were implemented on FPGA using Xilinx System Generator and XUP Virtex-II Pro development board.
引用
收藏
页码：459 / 462
页数：4
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