Power grid planning for microprocessors and SOCS

被引：0

作者：

Zhu, QK ^{[1
]}

Ayers, D ^{[1
]}

机构：

[1] Matrix Semicond Inc, Santa Clara, CA USA

来源：

6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes power grid planning methodology for high-performance microprocessors and SOC chips. It shows how to estimate currents from an existing chip to a new chip. The power grid planning and pre-layout simulation becomes important for time to market of chip design. We will discuss the current scaling technique and one SOC design example. More details on the methodology can be found in [9].

引用

页码：352 / 356

页数：5

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