Wideband multi-bit third-order sigma-delta ADC for wireless transceivers

被引：0
|
作者：
Kim, SH [1 ]
Choi, SW [1 ]
Kim, DY [1 ]
机构：
[1] Chonbuk Natl Univ, Div Elect & Informat Engn, Jeonju, South Korea
来源：
2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/ICASIC.2003.1277642
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a multi-bit sigma-delta data converter with third-order 3-bit topology. This converter can achieve high resolution with a lower order modulator and lower oversampling ratio than single-bit converter. The dynamic element matching (DEM) algorithm is designed in such a way as to minimize delay within the feedback loop of the sigma-delta ADC. The behavioral model is used to simulate the designed sigma-delta data converter. The designed ADC achieves 14-bit resolution. a peak SNR of 87dB within a 1 MHz signal baseband at a clock rate of 50MHz.
引用
收藏
页码：689 / 692
页数：4
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