Chip scale packaging solution with the flip-chip technologies for CMOS image sensor

Chip scale package with the flip-chip technologies on the optical devices, CMOS image sensor (CIS), has been developed for mobile product with camera module built-in. Flip-chip bumping technologies may be driven by size reduction as well as cost effectiveness compared with conventional packaging. In the study, gold and solder bumping technologies on the CIS device have been studied in terms of process, reliabilities and mass produce. In terms of the process of bumping technologies, the thin metal deposition process was designed to reduce the stress level for the damage-free wafer surface of various devices, especially image sensor device and rerouted wafers, regardless of bumping types. The assembly process of gold bumped CMOS image sensor device was developed by using flip-chip bonding with the anisotropic conductive material. Gold bumping technology has been found as a very stable and clean bumping solution into the image sensor devices. In solder bumping on the CIS device, very specific process design and material in the reshaping of original pad was considered and the process design of mushroom-shaped solder plating has been more fitted to introduce precise control in height and composition. In the assembly of solder of solder bumped CIS, interconnection of chip to substrate was accomplished by using controlled NCP process without damage onto pixel area. Assembly process with fluxless bonding process was reviewed as a clean bumping solution. Direct bumping technologies on image sensor device have been qualified and proven to be suitable to chip scaled optical package for mobile product. The technology of SiP (System in Package) will be discussed as a next generation of optical packaging.