A high speed programmable focal-plane SIMD vision chip

A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 x 64 pixel proof-of-concept chip was fabricated in a 0.35 mu m standard CMOS process, with a pixel size of 35 mu m x 35 mu m. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000-5,000 fps.