Verifying timing consistency in formal specifications

被引：1
|
作者：
Bartos, T
Fristacky, N
机构：
[1] Slovak Technical University, Bratislava
[2] Department of Computer Science, Slovak Technical University, Bratislava
[3] Dept. of Comp. Sci. and Engineering, Slovak Technical University, Fac. Elec. Eng. and Info. Technol., Bratislava
[4] IFIP TC-10, IEEE
[5] Slovak Tech. University, Bratislava, 812 19 Bratislava
来源：
IEEE DESIGN & TEST OF COMPUTERS | 1996年 / 13卷 / 01期
关键词：
D O I：
10.1109/54.485778
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The authors' algorithm formally verifies the rule set that expresses timing discipline in digital system specifications. Their algorithm is based on a higher level behavioral specification model and concerns formal consistency verification at the design level of the system specification development procedure.
引用
收藏
页码：8 / 15
页数：8
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