Run-Time Adaptive Performance Compensation using On-chip Sensors

被引:0
|
作者
Hashimoto, Masanori [1 ]
机构
[1] Osaka Univ, Dept Informat Syst Engn, Suita, Osaka 565, Japan
关键词
BODY BIAS; VOLTAGE;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper discusses run-time adaptive performance control with on-chip sensors that predict timing errors. The sensors embedded into functional circuits capture delay variations due to not only die-to-die process variation but also random process variation, environmental fluctuation and aging. By compensating circuit performance according to the sensor outputs, we can overcome PVT worst-case design and reduce power dissipation while satisfying circuit performance. We applied the adaptive speed control to subthreshold circuits that are very sensitive to random variation and environmental fluctuation. Measurement results of a 65nm test chip show that the adaptive speed control can compensate PVT variations and improve energy efficiency by up to 46% compared to the worst-case design and operation with guardbanding.
引用
收藏
页数:6
相关论文
共 50 条
  • [1] Run-time adaptive on-chip communication scheme
    Al Faruque, Mohammad Abdullah
    Ebi, Thomas
    Henkel, Joerg
    [J]. IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 26 - 31
  • [2] Run-Time Adaptable On-Chip Thermal Triggers
    Kumar, Pratyush
    Atienza, David
    [J]. 2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011,
  • [3] On-chip communication in run-time assembled reconfigurable systems
    Sedcole, Pete
    Cheung, Peter Y. K.
    Constantinides, George A.
    Luk, Wayne
    [J]. 2006 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING AND SIMULATION, PROCEEDINGS, 2006, : 168 - +
  • [4] Run-time loop restructuring for on-chip parallel processor
    Tamatsukuri, J
    Matsumoto, T
    Hiraki, K
    [J]. INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-IV, PROCEEDINGS, 1998, : 1489 - 1496
  • [5] Run-time power gating of on-chip routers using look-ahead routing
    Matsutani, Hiroki
    Koibuchi, Michihiro
    Wang, Daihan
    Amano, Hideharu
    [J]. 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 519 - +
  • [6] Adaptive Performance Compensation with On-Chip Variation Monitoring
    Hashimoto, Masanori
    Fuketa, Hiroshi
    [J]. 2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
  • [7] Evaluation and run-time optimization of on-chip communication structures in reconfigurable architectures
    Murgan, T
    Petrov, M
    Ortiz, AG
    Ludewig, R
    Zipf, P
    Hollstein, T
    Glesner, M
    Oelkrug, B
    Brakensiek, J
    [J]. FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2003, 2778 : 1111 - 1114
  • [8] A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs
    Sharma, Dimple
    Kirischian, Lev
    [J]. INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING, 2021, 2021 (2021)
  • [9] Energy Efficient On-Chip Power Delivery with Run-Time Voltage Regulator Clustering
    Pathak, Divya
    Hajkazemi, Mohammad Hossein
    Tavana, Mohammad Khavari
    Homayoun, Houman
    Savidis, Ioannis
    [J]. 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 1210 - 1213
  • [10] Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers
    Thakkar, Ishan G.
    Chittamuru, Sai Vineel Reddy
    Pasricha, Sudeep
    [J]. 2016 TENTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2016,