An efficient rectilinear Steiner tree algorithm for VLSI global routing

As we move to deep sub-micron designs below 0.18 microns, the delay of a circuit, as well as power dissipation and area, is dominated by interconnections between logical elements (i.e. transistors)[1]. The focus of this paper is on the global routine, problem. Both global and channel routing are NP-hard[2]; therefore, all existing solution methodologies are heuristics. The main aim is to develop an efficient K Rectilinear Steiner Trees (K-RST) algorithm. A k-RST routine is developed to generate a set of rectilinear Steiner trees for each net. The K-RST uses local tree segment transformations to ensure that there is no duplication of routing trees for a net. The shortest tree for a net is in general 11 % shorter than that of the minimal spanning tree, which leads to area savings.