Compact Associative Memory for AER Spike Decoding in FPGA-Based Evolvable SNN Emulation

被引：2

作者：

Zapata, Mireya ^{[1
]}

Madrenas, Jordi ^{[1
]}

机构：

[1] Univ Politecn Cataluna, Dept Elect Engn, Jordi Girona 1-3,Edif C4, ES-08034 Barcelona, Catalunya, Spain

来源：

ARTIFICIAL NEURAL NETWORKS AND MACHINE LEARNING - ICANN 2016, PT I | 2016年 / 9886卷

关键词：

Associative memory; SNN; AER; Digital neuromorphic systems; Evolvable connections;

D O I：

10.1007/978-3-319-44778-0_47

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A spike decoding scheme for Address Event Representation (AER)-based transmission in Spiking Neural Network (SNN) emulators is introduced. The proposed scheme is a modified associative memory based on an efficient use of BRAM, supporting connectivity upgrade in real-time for hardware implementations of evolutionary networks. After analysing the different options and selecting the most efficient one, a prototype example based on FPGA is provided together with a novel hashing technique to demonstrate a compact on-chip solution for implementing inter-chip connectivity in SNN.

引用

页码：399 / 407

页数：9

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