40 nm UltralowPower ChargeTrap Embedded NVM Technology for IoT Applications

被引：0

作者：

Kouznetsov, I. ^{[1
]}

Ramkumar, K. ^{[1
]}

Prabhakar, V. ^{[1
]}

Hinh, L. ^{[1
]}

Shih, H. M. ^{[1
]}

Saha, S. ^{[1
]}

Govindaswamy, S. ^{[1
]}

Amundson, M. ^{[1
]}

Dalton, D. ^{[1
]}

Phan, T. ^{[1
]}

Luzada, Z. ^{[1
]}

Raghavan, V. ^{[1
]}

Agrawal, V. ^{[1
]}

Donnelly, K. ^{[1
]}

Shih, P. C. ^{[2
]}

Huang, C. C. ^{[2
]}

Lee, K. L. ^{[2
]}

Wang, C. H. ^{[2
]}

Huang, C. H. ^{[2
]}

Lin, C. H. ^{[2
]}

Sheu, Y. K. ^{[2
]}

机构：

[1] Cypress Semicond Inc, San Jose, CA 95134 USA

[2] United Microelect Corp, Tainan, Taiwan

来源：

2018 IEEE 10TH INTERNATIONAL MEMORY WORKSHOP (IMW) | 2018年

关键词：

Nonvolatile memory; embedded; IoT; charge-trap; SONOS; ultralow-power;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 40 nm charge-trap embedded NVM technology is presented which is operational at the main power supply of 0.81 to 1.21 V. It is based on SONOS and requires only five extra masking steps beyond standard CMOS. A product-ready 8Mb macro is used to demonstrate technology capabilities. Key features are 25 ns read access time in the 0.99 to 1.21 V supply range and very low current consumption. The macro provides several power-saving modes, 100k write cycles and 10-year data retention for application in consumer and industrial SoCs.

引用

页码：187 / 190

页数：4

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