A programmable 512 GOPS stream processor for signal, image, and video processing

被引：33

作者：

Khailany, Brucek K. ^{[1
]}

Williams, Ted ^{[1
]}

Lin, Jim ^{[1
]}

Long, Eileen Peters ^{[1
]}

Rygh, Mark ^{[1
]}

Tovey, DeForest W. ^{[1
]}

Dally, William J. ^{[1
]}

机构：

[1] Stream Processors Inc, Sunnyvale, CA 94085 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2008年 / 43卷 / 01期

关键词：

digital signal processor (DSP); H.264; stream processing; video encoding;

D O I：

10.1109/JSSC.2007.909331

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 34-million transistor stream processor system-on-chip (SoC) for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores, and I/Os. Implemented in a 0.13 mu m CMOS technology, sixteen 800 MHz data-parallel lanes combine to deliver performance of 512 8-bit GOPS or 256 16-bit GOPS, or 128 billion 16-bit multiply-accumulates per second GMACs), with a power efficiency of 82 pJ/MAC.

引用

页码：202 / 213

页数：12

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