A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML

被引：0

作者：

Centurelli, Francesco ^{[1
]}

Scotti, Giuseppe ^{[1
]}

Trifiletti, Alessandro ^{[1
]}

Palumbo, Gaetano ^{[2
]}

机构：

[1] Univ Rome Sapienza, DIET Dept, Rome, Italy

[2] Univ Catania, DIEEI Dept, Catania, Italy

来源：

2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2021年

关键词：

DESIGN;

D O I：

10.1109/ISCAS51556.2021.9401445

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Current Mode Logic (FMCML) and an analytical design strategy to optimize its performance are presented. To validate the proposed models and design procedures we have used a 28nm, Fully Depleted Silicon on Insulator (FDSOI), CMOS technology to design and simulate a divide-by-8 circuit. The designed frequency divider exhibits a maximum operating frequency of about 15GHz with a power consumption of only 110.W thus confirming the advantages of the proposed approach.

引用

页数：5

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