Calculation of intermodulation distortion in CMOS transconductance stage

被引：0
|
作者：
Liu, L [1 ]
Wang, ZH [1 ]
Li, GL [1 ]
机构：
[1] Tsing Hua Univ, Dept Elect Engn, Beijing 100084, Peoples R China
来源：
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The linearity of the transconductance stage is of major concern in the design of some analog circuits. In this paper, Volterra series expansion is used to compute the intermodulation distortion of high frequency CMOS transconductance stage with source degeneration resistor. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
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页码：3700 / 3703
页数：4
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