A 6GHz Direct Digital Synthesizer MMIC with Nonlinear DAC and Wave Correction ROM

被引：0
|
作者：
Wu, Danyu [1 ]
Chen, Gaopeng [1 ]
Chen, Jianwu [1 ]
Liu, Xinyu [1 ]
Zhao, Lixin [1 ]
Jin, Zhi [1 ]
机构：
[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China
来源：
2010 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS RFIC SYMPOSIUM | 2010年
关键词：
direct digital synthesizer (DDS); sine-weighted DAC; wave correction ROM (WCR); emitter coupled logic (ECL); digital-to-analog converter (DAC); CLOCK FREQUENCY;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes a new DDS architecture combined with Nonlinear DAC and Wave-Correction-ROM (WCR) which shows both high operating speed and accuracy. Based on this architecture, a 6GHz 8-bit DDS MMIC is designed and fabricated in 60GHz GaAs HBT Technology. The DDS MMIC includes 8-bit pipeline accumulator, an 8x8x3bits WCR, two combined DACs and an analog Gilbert Cell for sine-wave generation with 8-bit amplitude resolution. The DDS chip is tested in on-wafer measurement system. The measured spurious free dynamic range (SFDR) is 33.96dBc with 2.367GHz output under a 6GHz maximum clock (FCW=0x65). It shows an average SFDR of 37.5dBc and the worst case SFDR of 31.4dBc (FCW=0x70) within the whole Nyquist band under a 5GHz clock frequency. The whole chip occupies 2.4x2mm(2) of area consuming 3.27W of power from a single -4.6Vpower supply.
引用
收藏
页码：421 / 424
页数：4
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