A massively scaleable decoder architecture for low-density parity-check codes

被引：0

作者：

Selvarathinam, A ^{[1
]}

Choi, G ^{[1
]}

Narayanan, K ^{[1
]}

Prabhakar, A ^{[1
]}

Kim, E ^{[1
]}

机构：

[1] Texas A&M Univ, Dept Elect Engn, College Stn, TX 77843 USA

来源：

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS | 2003年

关键词：

LDPC decoder; parallel architecture; VLSI; BER/FER; hardware scaling;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to achieve a throughput of 100 Gbps. Simulation results show that this throughput is achieved without significant bit-error performance degradation.

引用

页码：61 / 64

页数：4

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