Improving single-thread fetch performance on a multithreaded processor

被引:0
|
作者
Moure, JC [1 ]
Garcia, RB [1 ]
Rexachs, DI [1 ]
Luque, E [1 ]
机构
[1] Univ Autonoma Barcelona, Comp Architecture & Operat Syst Grp, E-08193 Barcelona, Spain
关键词
D O I
10.1109/DSD.2001.952344
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Multithreaded processors, by simultaneously using both the thread-level parallelism and the instruction-level parallelism of applications, achieve larger instruction per cycle rates than single-thread processors. On a multi-thread workload, a clustered organization maximizes performance. On a single-thread workload, however, all but one of the clusters are idle, degrading single-thread performance significantly. Using a clustered multithreaded processor optimized for multi-thread performance as a baseline, we propose and analyze several mechanisms and policies to improve single-thread execution exploiting the existing hardware without a significant multi-thread performance loss. We focus on the fetch unit, which is maybe the most performance-critical stage. Essentially, we analyze three ways of exploiting the idle fetch clusters: allowing a single thread accessing its neighbor clusters, use the idle fetch clusters to provide multiple-path execution, or use them to widen the effective single-thread fetch block.
引用
收藏
页码:390 / 395
页数:6
相关论文
共 50 条
  • [1] SINGLE-THREAD NUTS
    不详
    MACHINE DESIGN, 1973, 45 (28) : 68 - 69
  • [2] SINGLE-THREAD ENGAGING NUTS
    SEITZ, WA
    PETRUS, S
    MACHINE DESIGN, 1969, 41 (21) : 48 - &
  • [3] SINGLE-THREAD ENGAGING NUTS
    SEITZ, WL
    PETRUS, S
    MACHINE DESIGN, 1967, 39 (14) : 52 - &
  • [4] Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance
    Kondguli, Sushant
    Huang, Michael
    IEEE COMPUTER ARCHITECTURE LETTERS, 2018, 17 (02) : 205 - 208
  • [5] Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance
    Kondguli, Sushant
    Huang, Michael
    TWENTY-FOURTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS (ASPLOS XXIV), 2019, : 687 - 700
  • [6] Parallel single-thread strategies in scheduling
    Bozejko, Wojciech
    Pempera, Jaroslaw
    Smutnicki, Adam
    ARTIFICIAL INTELLIGENCE AND SOFT COMPUTING - ICAISC 2008, PROCEEDINGS, 2008, 5097 : 995 - 1006
  • [7] COMPARISON OF MODELS FOR SINGLE-THREAD STREAMS
    SHIMIZU, Y
    SMITH, JD
    NELSON, JM
    SEDIMENT TRANSPORT MODELING: PROCEEDINGS OF AN INTERNATIONAL SYMPOSIUM, 1989, : 524 - 529
  • [8] Maurer computers with single-thread control
    Bergstra, Jan A.
    Middelburg, Cornelis A.
    FUNDAMENTA INFORMATICAE, 2007, 80 (04) : 333 - 362
  • [9] On networking multithreaded processor design:: Hardware thread prioritization
    Döring, A
    Gabrani, M
    Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 2003, : 520 - 523
  • [10] Analysis of single-thread worms with discontinuous loops
    Kochetov V.I.
    Klinkov A.S.
    Sokolov M.V.
    Chemical and Petroleum Engineering, 2004, 40 (3-4) : 128 - 133