A fast sequential learning technique for real circuits with application to enhancing ATPG performance

被引：0
|
作者：
El-Maleh, A [1 ]
Kassab, M [1 ]
Rajski, J [1 ]
机构：
[1] Mentor Graph Corp, Wilsonville, OR 97070 USA
来源：
1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS | 1998年
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times.
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收藏
页码：625 / 631
页数：7
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