High Speed Low Cost Implementation of Advanced Encryption Standard on FPGA

Cryptography plays an important role in the security of data. It enables us to store sensitive information or transmit it across insecure networks so that unauthorized persons cannot read it. The need for privacy has become a major priority and important for communication in all fields. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications The urgency for secure exchange of digital data resulted in large quantities of different encryption algorithms which can be classified into two groups: asymmetric encryption algorithms (with public key algorithms) and symmetric encryption algorithms (with private key algorithms) [1]. In this paper, we use FPGA chips to realize high data throughput AES hardware architecture is proposed by partitioning the ten rounds into sub-blocks of repeated AES modules. The blocks are separated by intermediate buffers providing a complete ten stages of AES pipeline structure. This paper presents Implementation of 128 bit-key AES cipher. The design target was optimization of speed and cost. A focus on low cost resulted in a design well-suited for SoC implementations