Design of Nonbinary LDPC Codes Based on Message-Passing Algorithms

被引:3
|
作者
Cho, Sunghye [1 ,2 ]
Cheun, Kyungwhoon [3 ]
Yang, Kyeongcheol [1 ]
机构
[1] Pohang Univ Sci & Technol, Dept Elect Engn, Pohang 37673, South Korea
[2] Samsung Elect Co Ltd, DRAM Design Team, Memory Business, Suwon 16677, South Korea
[3] Samsung Elect Co Ltd, Networks Business, Res & Dev Team, Suwon 16677, South Korea
基金
新加坡国家研究基金会;
关键词
Nonbinary low-density parity-check codes; full rank condition; message-passing algorithm; counting cycles; error floor; design method; PARITY-CHECK CODES; MATRICES; GRAPHS; GF(Q);
D O I
10.1109/TCOMM.2018.2849076
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Short cycles in a nonbinary low-density parity-check (NB-LDPC) code may he even more harmful to its performance if they do not satisfy the so-called full rank condition (FRC). This is because they may induce low-weight codewords or absorbing sets in that case. Thus, it is important to count the number of short cycles not satisfying the FRC as well as the number of short cycles for analyzing the performance of an NB-LDPC code. In this paper, we first develop a novel message-passing algorithm and identify how it is related to the FRC. We then propose a low-complexity algorithm for counting the number of short cycles not satisfying the FRC in an NB-LDPC code, as well as the number of short cycles. Finally, we propose a low-complexity algorithm for designing an NB-LDPC code with low error floor. Depending on the modulation scheme, the codes constructed by the proposed design algorithm have similar or slightly worse performance, compared with those constructed via the method by Poulliat et al. However, the proposed design algorithm does not require a cycle enumeration algorithm with high complexity, and therefore is feasible even in the case of large code length, say >= 5000.
引用
收藏
页码:5028 / 5040
页数:13
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