Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors

被引:0
|
作者
Velev, MN [1 ]
Bryant, RE [1 ]
机构
[1] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15213 USA
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中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SAT-checker that significantly outperforms the rest. We evaluate ways to enhance its performance by variations in the generation of the Boolean correctness formulas We reassess optimizations previously used to speed up the formal verification and probe future challenges.
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页码:226 / 231
页数:6
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