Design and Implementation of Data Acquisition System Based on FPGA and High-speed AD

被引:0
|
作者
Li, Zhi [1 ]
Chen, Dahua [1 ]
机构
[1] Guilin Univ Elect Technol, Sch Elect Engn & Automat, Guilin 541004, Peoples R China
关键词
FPGA; high-speed AD; analog channels; LVDS signal;
D O I
10.4028/www.scientific.net/AMM.556-562.1515
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
High speed analog signals output by test object in the field of testing and controlling is typical. This paper designed a high-speed AD data acquisition system responding to this situation. In the design of the system, data is first conditioned by the analog channel. FPGA is then employed to receive, decelerate, reorganize and store the high-speed LVDS data output by AD. Data is displayed in computer after being collected by ARM from FGPA. Real circuit designing demonstrated that the high-speed data acquisition system of AD based on 100M bandwidth of analog channel is workable.
引用
收藏
页码:1515 / 1519
页数:5
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