Voltage and Return Plane Bounce Affecting Digital Components Using Different Printed Circuit Board Edge Termination Methodologies

被引：3

作者：

Montrose, Mark I. ^{[1
]}

机构：

[1] Montrose Compliance Serv Inc, Santa Clara, CA 95051 USA

来源：

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY | 2011年 / 53卷 / 03期

关键词：

Ground bounce; power bounce; power distribution network (PDN); printed circuit board (PCB); signal integrity (SI); simultaneously switching noise (SSN);

D O I：

10.1109/TEMC.2011.2141997

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper illustrates effects of board edge termination related to development of either voltage or return plane bounce exceeding operational margin levels of digital components at multiple locations within a printed circuit board (PCB). We study an actual problem encountered by design engineers using a worse-case configuration. This paper also explains how power and/or return bounce is developed. Lack of optimal plane termination at the physical edges of a PCB will exacerbate plane bounce. In addition, a solution that prevents this problem is provided in Section VIII.

引用

页码：802 / 805

页数：4

共 2 条

[1] Power and ground bounce effects on component performance based on printed circuit board edge termination methodologies
Montrose, Mark I.
Liu En-Xiao
[J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY: WORKSHOP AND TUTORIAL NOTES, VOLS 1-3, 2007, : 576 - +
[2] Analysis on the effectiveness of printed circuit board edge termination using discrete components instead of implementing the 20-H rule
Montrose, MI
Enxiao, L
Li, EP
[J]. 2004 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SYMPOSIUM RECORD 1-3, 2004, : 45 - 50

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