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A recent article (Reference 1) posed three questions regarding 3-D ICs: What are 3-D ICs, are they real, and what difference do they make? The answers to these questions may vary, but the semiconductor industry is increasingly adding a vertical that is, stacked alternative to traditional 2-D Moore's Law scaling (Reference 2). Reducing the length of interconnects between ICs can make a big difference in performance, power, and package size in mobile-system applications major drivers for 3-D ICs. Combining a mobile-processor die with a separate memory chip is a natural development for a 3-D structure. For example, Samsung Electronics recently introduced a 3-D IC, which the company stacks with a memory chip that connects using TSVs (through-silicon vias) vertical, metallized holes in the silicon die that create connections on both the top and the bottom of a chip (Figure 1). TSV technology enables a wide I/O-memory interface, reducing power by as much as 75% versus other approaches as a result of the lower load capacitance of interconnect and I/O circuits.