High PSRR CMOS voltage reference for negative LDOs

被引：0

作者：

Stanescu, C ^{[1
]}

Caracas, C ^{[1
]}

Panaite, D ^{[1
]}

Aungurencei, G ^{[1
]}

Russell, A ^{[1
]}

Georgescu, S ^{[1
]}

机构：

[1] Catalyst Semicond Romania SRL, Bucharest, Romania

来源：

2004 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1AND 2, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper presents a CMOS voltage reference built within a negative LDO processed in a double-metal 0.8 mu m CMOS technology. The reference consumes 12 mu A, and delivers a stable output voltage of -1.2V. Power Supply Rejection Ratio is 86dB at low frequencies, while TC is within +/- 50ppm/C-0, and un-trimmed V-REF spread 60mV(+/- 3 sigma).

引用

页码：311 / 314

页数：4

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