Linearity testing of precision analog-to-digital converters using stationary nonlinear inputs

As the performance of Analog-to-Digital Converters continues to improve, it is becoming more challenging and costly to develop sufficiently fast and low-drift signal generators that are adequately more linear than the ADC for the purpose of linearity testing. This work relaxes the linearity requirements on the signal generators used for ADC testing by alternatively employing. multiple non-linear inputs. Assuming minimal prior knowledge of the input non-linearity, a testing methodology is introduced that is based upon first identifying and computationally removing the source non-linearity and then accurately estimating the ADC linearity. Production test hardware is used for validating the performance of this testing methodology using a high performance 16-bit SAR ADC as a test vehicle. Integral linearity error readings are identified to well within the +/-2 LSB range of the device specification by using only 8-bit linear inputs. This approach provides an enabling technology for cost-effective full-code testing of high performance ADCs in production test and for a cost-effective implementation of built-in self-test (BIST).