Measurement of De-assertion Threshold of Power-on-Reset Circuits

被引：0

作者：

Wadhwa, Sanjay Kumar ^{[1
]}

Tripathi, Avinash Chandra ^{[1
]}

机构：

[1] Freescale Semicond India Pvt Ltd, Plot 2&3,Sect 16A, Noida, UP, India

来源：

2015 19TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT) | 2015年

关键词：

power on reset; de-assertion threshold; low power analog;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A test circuit for measuring the de-assertion threshold of a Power-on-Reset (POR) circuit is presented. With the help of the test circuit, POR de-assertion voltage can be measured without requiring a dedicated analog pad or a supply voltage higher than the POR supply voltage. The test circuit does not impact the normal mode of operation of POR and the area and power overhead due to the addition of the test circuit are minimal. The test circuit has been designed and simulated in 28nm CMOS technology. The simulation results show that the maximum error in de-assertion threshold measurement is less than +/-0.5%.

引用

页数：4

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