Design and Implementation of Adaptive Binary Divider for Fixed-Point and Floating-Point Numbers

Binary division operation has immense importance in the field of engineering science. Inherently, division operation is a sequential operation, making it more expensive in terms of computational complexity and latency compared with other mathematical operations likemultiplication and addition. Thiswork proposes a novel iterative binary division method with the goal of reducing the delay in its hardware implementation. The hardware circuits are designed using Verilog HDL and verified on Xilinx FPGA. This work also presents a study of area, power and delay of the proposed method for different specifications. At UMC 40nm technology node, the 32-bit radix-16 fixedpoint divider circuit requires 3938 mu m(2) area with a dynamic power consumption of 2.82 mu W/MHz. It has a latency of 2-9 clock cycles with a critical path delay of 4.97 ns. This work is further extended to design a single-precision floating-point divider. The divider is implemented with an area of 3353 mu m(2), power dissipation of 2.76 mu W/MHz and critical path delay of 4.83 ns.