Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression

Intracranial recording of brain activity is one of the key tools in understanding brain functions and treating some severe neurological diseases and disorders. Recent neural recording implants entail hundreds of channels and transmitting data off-chip is becoming more challenging and critical due to limited on-chip power budget and multi-channel high data rate. This paper proposes a single-channel ultra-low-power hardware accelerator for adaptive neural signal lossless compression. It consists of modified second-order differential pulse code modulation (DPCM) and an adaptive encoding engine. In this work, the neural signal is first decorrelated and condensed around zero. Then, an adaptive Golomb coding algorithm is proposed to compress data based on optimal parameters obtained from the signals in real-time. The simulation results show that the average space saving ratio (SSR) is 61.84%. The proposed design is implemented in 28nm CMOS technology and occupies an area of 792.4 mu m(2) and consumes 1.05 mu W at a frequency of 5MHz which outperforms the state-of-the-art lossless designs.