SPARC64 XIFX: FUJITSU'S NEXT-GENERATION PROCESSOR FOR HIGH-PERFORMANCE COMPUTING

被引：6

作者：

Yoshida, Toshio ^{[1
]}

Hondou, Mikio ^{[2
]}

Tabata, Takekazu ^{[3
]}

Kan, Ryuji ^{[4
]}

Kiyota, Naohiro ^{[4
]}

Kojima, Hiroyuki ^{[4
]}

Hosoe, Koji ^{[5
]}

Okano, Hiroshi ^{[6
]}

机构：

[1] Fujitsu, Next Generat Tech Comp Unit, LSI Dev Div, Minato, Tokyo, Japan

[2] Fujitsu, Next Generat Tech Comp Unit, Minato, Tokyo, Japan

[3] Fujitsu, Enterprise Server Business Unit, Proc Dev Div, Minato, Tokyo, Japan

[4] Fujitsu, Enterprise Server Business Unit, Minato, Tokyo, Japan

[5] Fujitsu, Next Generat Tech Comp Unit, Syst Dev Div, Minato, Tokyo, Japan

[6] Fujitsu Labs, Server Technol Lab, Minato, Tokyo, Japan

来源：

IEEE MICRO | 2015年 / 35卷 / 02期

关键词：

auto-parallelization; high performance computing; Hybrid memory cube; instruction set architecture; microprocessor; out of order; Sparc; supercomputer; Tofu interconnect;

D O I：

10.1109/MM.2015.11

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Sparc64 Xifx, Fujitsu's latest high-performance computing processor, includes a 34-core processor and achieves 1.1 teraflops of peak performance. This chip is designed for massive parallel supercomputer systems that realize high performance for a range of real applications. As groundwork for exascale supercomputing, it made major technological changes from the previous sparc64 processor in the instruction set architecture, microarchitecture, memory modules, and embedded interconnect.

引用

页码：6 / 14

页数：9

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